The present invention generally relates to testing of transceivers. More specifically, the present invention relates to a method and device for implementing a built-in self-test for multi-channel transceivers.
In modern data networks, data are typically transmitted in high volume at a high transmission rate over long distances. Since the quality of the data signals degrades proportionally with the length of a transmission line, circuits known as transmitter-receivers or transceivers are usually placed along a transmission line at certain predetermined locations to boost or rebroadcast the data signals to maintain their quality. Thus, due to the nature of their operation, transceivers need to be monitored and tested to ensure that the boosted data signals they produce are indeed accurate versions of the original signals.
FIG. 1 is a simplified block diagram showing a conventional transceivers circuitry which typically includes a clock/data recovery circuit 10, a demultiplexer 12 and a multiplexer 14. The testing of the transceiver is usually done in the following manner. External circuitry 8 produces a test signal as input to the multiplexer 14. The test signal is transmitted as a frame via multiple input channels 18 into the multiplexer 14. The test signal is then serialized by the multiplexer 14 and transmitted through a single multiplexer output channel 16 to the clock/data recovery circuit 10. The clock/data recovery circuit 10 recovers the test signal and feeds the recovered test signal into the demultiplexer 12. One function of the demultiplexer 12 is to parse the recovered data and direct them into various output channels 20 (i.e. deserialize the data stream). The collective output from these various output channels 20 is then checked by external circuitry 6 against the test signal to determine whether the transceiver is functioning properly.
During the course of transmission from the multiplexer 14 through the clock/data recovery circuit 10 to the demultiplexer 12, it is not unusual to have a collective shift in the test signal causing the relative position of the entire test signal to change without affecting the integrity of the test signal. In other words, the beginning of the test signal frame which is transmitted via one input channel of the multiplexer 14 may not always come out at precisely the corresponding output channel of the demultiplexer 12. For example, the beginning of the test signal frame transmitted via the first multiplexer input channel may not come out at the corresponding first demultiplexer output channel. Thus, while the contents or bits within the frame may have been transmitted correctly, a shift in the frame position may lead to an erroneous conclusion that the transceiver is malfunctioning. In order to avoid this situation, a “framer” circuit, which is commonly known in the art, is typically employed to accurately align or “frame” the initial test signal and the output received from the demultiplexer 12 before the two signals are compared.
Framer circuits that must keep track of signal timing for alignment purposes tend to be quite complex. Due to their complexity, such circuits are relatively expensive. Furthermore, such circuits typically occupy large silicon area and consume a relatively large amount of power rendering it difficult to have such circuit incorporated with a transceiver in an integrated circuit. Therefore, it would be desirable to provide a method and device for implementing a built-in self-test for multi-channel transceivers which is cost effective and capable of being integrated with a transceiver in an integrated circuit.